There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. This trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device features along with the pitch of the device features. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and, accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.
High numerical aperture (NA) 193 nanometer (nm) optical projection stepper/scanner systems in combination with advanced photoresist (or resist) processes now are capable of routinely resolving isolated and dense line/space resist features having CDs and pitches, respectively, well below the wavelength of the exposing radiation. However, to meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These methods include double patterning techniques (DPT) such as litho/freeze/litho/etch (LFLE) processes in which device patterns having features designed with a potentially unresolvable pitch are decomposed or “split” into two or more complementary, and more easily resolved patterns, each containing features with a relaxed pitch. In LFLE, such pitch splitting is achieved by patterning a first layer of photoresist followed by “freezing” the resist features rendering them unaffected by a second patterning process used for imaging a second layer of photoresist. Other resolution-enhancing techniques include sidewall spacer lithography techniques often used, for example, in the fabrication of FinFET devices. Such processes generate a masking layer having high resolution lines with a narrow pitch that is ultimately used as an etch mask to form fin structures.
Resolution enhancement methods also include image reversal processes whereby an etch mask layer is fabricated having a tonality reverse that of patterned masking features formed by a previous lithography process. Image reversal processes may be useful for patterning inherently difficult-to-resolve features such as contact holes and narrow resist trenches by reversing the tonality of pillar and line features, respectively. This is because opaque pillar and line features from a brightfield (or positive tone) photomask generate a higher contrast aerial image than clear contact hole and space features from an analogous darkfield photomask having the same CD, and thus are inherently more resolvable. However, conventionally a single image reversal process suitable for reversing the tone of both resist line and pillar features and compatible with both LFLE and sidewall spacer lithography processes does not exist.
Accordingly, it is desirable to provide methods for fabricating semiconductor devices using an image reversal lithography technique that is suitable for reversing the tone of both resist line and pillar features and is compatible with both LFLE and sidewall spacer lithography processes. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.